1. Field of the Invention
The present invention relates to an electrically rewritable non-volatile semiconductor storage device and a method of manufacturing the same.
2. Description of the Related Art
Conventionally, LSIs are formed by integration of devices in a two-dimensional plane on the silicon substrate. Although the dimension for each device must be reduced (refinement) to increase memory storage capacity, recent years are facing challenges in such refinement from the viewpoint of cost and technology. Such refinement requires further improvements in photolithography technology. However, in currently available ArF immersion lithography technology, for example, the resolution limit has been reached around the 40 nm design rule and so EUV exposure devices have to be introduced for further refinement. However, the EUV exposure devices are expensive and infeasible in view of the costs. In addition, if such refinement is accomplished, it is assumed that physical improvement limit, such as in breakdown voltage between devices, would be reached unless driving voltage can be scaled, for example. Thus, it is likely that difficulties would be encountered in device operation itself.
Therefore, a large number of semiconductor storage devices have been proposed recently where memory cells are arranged in a three-dimensional manner to achieve improved integration of memory devices (see, Patent Document 1; Japanese Patent Laid-Open No. 2003-078044; Patent Document 2: U.S. Pat. No. 5,599,724; and Patent Document 3: U.S. Pat. No. 5,707,885).
One of the conventional semiconductor storage devices where memory cells are arranged in a three-dimensional manner uses transistors with cylinder-type structure (see, Patent Documents 1-3). Those semiconductor storage devices using transistors with cylinder-type structure are provided with multiple layers of polysilicon corresponding to gate electrodes and pillar-like columnar semiconductors. Each of the columnar semiconductors serves as a channel (body) part of each of the transistors. Tunnel insulation layers are provided around the columnar semiconductors. Charge accumulation layers for accumulating charges are further provided around the tunnel insulation layer. Moreover, block insulation layers are formed around the charge accumulation layers. Such configuration including polysilicon, columnar semiconductors, tunnel insulation layers, charge accumulation layers, and block insulation layers is referred to as a “memory string”.
When selection transistors are provided above and below the memory string, they are required to have good cut-off characteristics. On the other hand, in view of the yields and costs of the memory devices, it is desirable to use polysilicon for columnar semiconductor layers that represent the body parts of the selection transistors. In this case, however, it is more difficult to control the potential of the columnar semiconductor layers using the gate electrodes than when the columnar semiconductor layers are configured by single-crystal silicon, due to the existence of numerous interface (grain boundary) states in polysilicon. That is, there will be an issue of suppressing leakage current when polysilicon is used for the columnar semiconductor layers.